This invention relates generally to semiconductor integrated circuits and more particularly, it relates to a protection system for CMOS integrated circuits to prevent inadvertent damage caused by electrostatic discharge during manufacturing and throughout its product life.
It is generally known that the magnitude of an electric voltage allowed to be applied to an integrated circuit package is rather limited since the physical size of the integrated circuit package is fairly small. When the integrated circuit package is not being used, for example, in storage or handling, the external leads or pins thereof are susceptible to the build-up of a static charge thereon. If the integrated circuit package happens to come in contact with a ground potential, the accumulated static charges will flow to ground. Such static discharge can be of a catastrophic nature with sufficient energy to cause damage or even destroy the semiconductor element or chip mounted within the integrated circuit package.
In order to protect the semiconductor chip in the integrated circuit package from being destroyed when such static discharges occur, there has been provided in the prior art a protection element such as a p-n junction applied with a reverse bias, which breaks down when the semiconductor chip encounters an unexpectedly high voltage. However, these protection devices were only provided between either the input or output pins and a power supply pin. Thus, in such protection devices, the charges accumulated on either the input pins or output pins were discharged only when the power supply pin was made to come in contact with the ground potential. Accordingly, the prior art protection devices offered no protection when another input pin or output pin was the one referenced to ground. Also, no discharge path was provided for when the accumulated charges were applied on a power supply pin.
In actual practice, the build-up of such electrostatic charges could be applied on any one of the plurality of external pins of the integrated circuit package which typically has as many as forty leads. The discharging occurs when any one of the remaining pins comes into contact with the grounded potential. As a consequence, the discharging could occur, in essence, between any one of the pins and any one of the other remaining pins. As used herein, the pin on which the electrostatic charges are applied is referred to as the "pin zapped", and the pin coming into contact with the grounded potential is referred to as the "pin grounded".
It would therefore be desirable to provide a protection system for CMOS integrated circuits to prevent inadvertent damage caused by electrostatic discharge occurring between any pin and any other pin of the integrated circuit package. This is achieved in the present invention by the provision of low impedance parasitic clamps connected to each of the bonding pads which are connectible to external pins and a low impedance bus structure interlinking all of the clamps together.